1. Field of the Invention
The present invention relates to a bias generator for generating a bias to be applied in a semiconductor memory device, such as a flash memory, or the like, and to a method for controlling such a bias generator.
2. Description of the Prior Art
Flash memories, which form a class of nonvolatile semiconductor memory device, are roughly divided into floating gate flash memories, which have a conductive floating gate located between a control gate and a semiconductor substrate and surrounded by an oxide film, and MONOS flash memories, which have an insulation film between a control gate and a semiconductor substrate, the insulation film being formed by an oxide film, nitride film, and oxide film in this order from the lower layer to the upper layer, wherein charge trapped by the nitride film serves as memory information.
In the MONOS flash memory, the nitride film for trapping the charge is an insulation film, and therefore, locally trapping the charge is possible. Charges are accumulated at opposite sides of a trap layer, whereby memorization of two-bit information is possible using different regions of one memory cell. Thus, the MONOS flash memory has been joining the mainstream of the nonvolatile bulk memory.
FIG. 9 is a cross-sectional view of a MONOS flash memory cell which has a trap layer. The MONOS flash memory cell includes impurity diffusion regions 1902 and 1904 in the upper part of P-type semiconductor substrate 1900, which form N-type source or drain, and a first silicon oxide film 1906, a silicon nitride film 1908, a second silicon oxide film 1910, and a conductive control gate 1912 sequentially deposited on a channel region between the impurity diffusion regions 1902 and 1904.
The silicon nitride film 1908 works as a trap layer to retain information by means of trapping charge. Referring to FIG. 9, the silicon nitride film 1908 includes charge trapping regions 1914 and 1916 at opposite sides (i.e., two positions), with which retaining two-bit information in one memory cell is possible.
To locally trapping charges in two different regions of one memory cell, typical MONOS flash memories employ electron injection into the trap layer with channel hot electron for the data-writing mechanism (CHE writing) and hole injection by means of band-to-band tunneling injection (BTBT injection) for the data-erasing mechanism such that charges trapped at the opposite sides of the silicon nitride film 1908 are neutralized.
TABLE 1 shows the voltages applied to a MONOS memory cell in respective operation modes. In this example, the source and drain terminals have potential relationship and current direction in respective operation modes which are defined as reference. According to the terminal definition employed in this example, the source and drain terminals in the same memory cell are replaced by each other as the reading operation mode and the writing operation mode are switched from one to the other. The sense potential, which is the source potential during writing verification and erasure verification operations, refers to the potential at which a selection bit line constituting the source of a memory cell from which data is to be read is charged by the cell current of a selected memory cell.
TABLE 1SourceControl GateDrainReadingSense potential4V1.3 VWriting0 V10V4 V to 7 VWriting verificationSense potential6V1.3 VErasureFloat-4.5V4 V to 7 VErasure verificationSense potential3V1.3 V
In the writing operation, a high voltage of about 10 V is applied to the control gate for CHE writing while a stepped voltage, which is increased stepwise at every writing cycle from about 4 V to about 7 V, is applied to the drain. In the erasure operation, a negative voltage of about −4.5 V is applied to the control gate for BTBT injection, while a stepped voltage, which is increased stepwise at every erasure cycle from about 4 V to about 7 V, is applied to the drain. In the reading operation, to obtain a necessary cell current, a voltage of about 4 V is applied to the control gate while a voltage of about 1.3 V is applied to the drain.
FIG. 10 shows the timing of applying a voltage to the memory cell in the writing operation. At time t1, data-write signal Co_WE for controlling the writing operation transitions to “L” level so that the operation is set to the writing mode, and accordingly, control gate potential VCG is set to a high voltage of about 10 V. Then, at time t2 at which control gate potential VCG is set to about 10 V, drain potential VBL is set to about 4 V.
At time t3, data-write signal Co_WE transitions to “H” level to end one writing cycle. Accordingly, control gate potential VCG is set to a potential of about 6 V for verification of writing. The drain terminal, to which a potential of about 4 V is applied during the writing operation, is used as the source terminal during the writing verification operation, and source potential VBL is set to 0 V. The drain voltage unshown is set to a voltage of about 1.3 V.
In the writing verification operation, if the writing level is judged as being unreached, the writing cycle that starts at time t1 is repeated. In this process, drain potential VBL is set to a higher potential by one step.
Setting of the control gate potential in the writing operation thus occurs prior to setting of the drain voltage such that the writing operation is started after the control gate potential is set to a target potential in order to prevent deterioration in endurance characteristics. The deterioration in endurance characteristics would occur if the writing operation be carried out in a transient potential state where the control gate potential rises so that an electron trapping region would be enlarged.
FIG. 11A shows a memory cell. FIG. 11B to FIG. 11D are circuit diagrams showing the types of charge pump circuits and regulators necessary for generating the potentials which are to be applied to the memory cell 1200 in respective operation modes shown in TABLE 1. In the writing verification and erasure verification operations illustrated in FIG. 11B, the potential of about 1.3 V which is to be applied to the drain is generated by a bit line potential generation circuit 1104 based on supply voltage (VDD) and applied via a reading bias transistor 1105. The gate voltage of about 4 V to 6 V is set by a gate potential regulator 1106 based on the HV potential generated by a HV charge pump circuit 1100 which is higher than the supply voltage.
In the writing operation illustrated in FIG. 11C, the stepped potential of about 4 V to 7 V which is to be applied to the drain is set by a drain potential regulator 1108 based on the HV potential generated by the HV charge pump circuit 1100. The control gate potential of about 10 V is derived from HHV potential generated by a HHV charge pump circuit 1102 which is higher than the potential generated by the HV charge pump circuit 1100.
In the erasure operation illustrated in FIG. 11D, the stepped potential of about 4 V to 7 V, which is to be applied to the drain, is set by the drain potential regulator 1108 based on the HV potential generated by the HV charge pump circuit 1100 as is in the writing operation. The potential of about −4.5 V which is to be applied to the control gate is generated by a negative potential generation circuit 1110.
FIG. 12 shows an example of the circuit structure of a flash memory 1300 which includes the MONOS cells shown in FIG. 9. The flash memory 1300 includes a memory cell array 1402 to which a virtual ground array (VGA) suitable to a bulk memory is applied.
The memory cell array 1402 is formed by memory cells arranged in an array of rows and columns. The control gates of the memory cells in the same rows are connected to common word lines WL0 and WL1. Any of the word lines is selected by a row decoder 1414 according to an input address. The sources and drains of the memory cells of the same rows are connected together and connected to bit lines BL0 to BL3. Any of the bit lines is selected by a column selection gate 1406 which is controlled based on selection signals YG0 to YG3 that the column decoder 1416 outputs according to the input address and by a source-drain selection gate 1407 which is controlled based on selection signals SD0 and SD1 that the source-drain decoder 1418 outputs according to the input address.
In the reading operation, writing verification operation and erasure verification operation, the operation of the HHV charge pump circuit 1102 and the negative potential generation circuit 1110 is halted so that the output potential of the HHV charge pump circuit 1102 is at the level of the supply potential, and the output potential of the negative potential generation circuit 1110 is at the level of the ground potential. The potential of about 4 V to 6 V which is to be applied to the control gate of a selected memory cell is set by the gate potential regulator 1106 based on the HV potential which is higher than the supply voltage generated by the HV charge pump circuit 1100. The multiplexer 1422 selects this potential and supplies the selected potential to the positive-side power supply node of the row decoder 1414, whereby the selected word line is set to the potential of about 4 V to 6 V. The potential of about 1.3 V, which is to be applied to the drain of the selected memory cell, is derived from a potential generated by the bit line potential generation circuit 1104 based on the supply voltage and is supplied to the selected memory cell via a reading bias transistor 1105, the source-drain selection gate 1407, and the column selection gate 1406. Reading of memory data from a memory cell is carried out by a sense amplifier 1408 comparing the potential of a bit line selected via the column selection gate 1406 and the source-drain selection gate 1407 with reference potential VREF. The result of the comparison, Sout, is output to an external device.
In the writing operation, the HV charge pump circuit 1100 and the HHV charge pump circuit 1102 are activated while the negative potential generation circuit 1110 is halted such that the output potential of the negative potential generation circuit 1110 is at the level of the ground potential. The potential of about 10 V, which is to be applied to the control gate of the selected memory cell, is derived from the output potential of the HHV charge pump circuit 1102 selected by the multiplexer 1422. The multiplexer 1422 supplies the selected potential to the positive-side power supply node of the row decoder 1414 as the potential of the selected word line. The potential of about 4 V to 7 V, which is to be applied to the drain of the selected memory cell, is derived from the output of a data writing circuit 1412 which receives a potential set by the drain potential regulator 1108 based on the output potential of the HV charge pump circuit 1100. The output of a data writing circuit 1412 is supplied to the selected bit line via the source-drain selection gate 1407 and the column selection gate 1406. Meanwhile, the supply voltage of the column decoder 1416 and the source-drain decoder 1418 is the output potential of the HHV charge pump circuit 1102 selected by a multiplexer 1424, and the selection control signal potential of the column selection gate 1406 and the source-drain selection gate 1407 is at the level of the output potential of the HHV charge pump circuit 1102. With this arrangement, the potential of about 4 V to 7 V which is the output of the data writing circuit 1412 can efficiently be transferred to the bit line. The source of the selected memory cell is grounded by making a switch 1410 conducting, the switch 1410 being connected to a selected bit line via the source-drain selection gate 1407 and the column selection gate 1406.
In the erasure operation, the HV charge pump circuit 1100, the HHV charge pump circuit 1102 and the negative potential generation circuit 1110 are activated. The negative potential of about −4.5 V which is to be applied to the control gate of the selected memory cell is derived from the output of the negative potential generation circuit 1110, which is supplied to the negative-side power supply node of the row decoder 1414 and set as the potential of the selected word line. The potential of about 4 V to 7 V which is to be applied to the drain of the selected memory cell is set by supplying the output of the data writing circuit 1412 to the selected bit line via the source-drain selection gate 1407 and the column selection gate 1406. The data writing circuit 1412 receives the potential set by the drain potential regulator 1108 that receives the output potential of the HV charge pump circuit 1100. Meanwhile, the supply voltage of the column decoder 1416 and the source-drain decoder 1418 is the output potential of the HHV charge pump circuit 1102 selected by the multiplexer 1424 as in the writing operation. The source of the selected memory cell is rendered floating by turning off the switch 1410 which is connected to the selected bit line via the source-drain selection gate 1407 and the column selection gate 1406.
The voltage generation control and timing control for switching of the charge pump circuits and multiplexers in the respective operation modes are realized based on an internal control signal output from a controller 1426.
Referring to FIG. 11C, the flash memory needs a plurality of higher voltages for rewriting operations and therefore requires a plurality of charge pump circuits, e.g., the HV charge pump circuit 1100, the HHV charge pump circuit 1102 and the negative potential generation circuit 1110. Thus, the size of the peripheral circuit other than the memory cell array is large as compared with the other memory types. Especially in a chip having a small memory capacity, the size occupancy of the peripheral circuit relative to the chip size is large, which constitutes a factor of an increase in cost. In view of such, in order to suppress the increase in chip size because of the charge pump circuits in the nonvolatile memory, Japanese Laid-Open Patent Publications Nos. 2001-338493, 2001-338493 and 2005-176590 disclose the techniques of generating a plurality of voltages by one charge pump circuit.